(a) Field of the Invention
The present invention relates to a time synchronized multi-processor system and a method for synchronizing multiple processor elements in the system to a time source so as to determine the absolute time that events occur in the system.
(b) Description of the Prior Art
Increasingly, large computer systems are being built using many individual processors running in parallel. Time synchronization of these multiple processors is needed.
Timing systems are known in the prior art. For example, U.S. Pat. No. 4,503,490 to Thompson illustrates a timing system for distributing clock signals in a synchronous processing system having plural processing sections. The timing system includes a central clock circuit and a plurality of section clock circuits. Each section clock circuit is located in and associated with a different one of the processing sections. Each section clock circuit is arranged to respond to a system clock signal for stepping through a plurality of states including a state common to the plurality of section clock circuits. An arrangement, responsive to the system clock signal, produces and transmits to the plurality of section clock circuits a synchronization signal that routinely sets the plurality of section clock circuits to the common state. The timing system further includes an arrangement for controlling suspension of processing in the plural processing sections.
U.S. Pat. No. 4,803,708 to Momose relates to a time of day coincidence system for coinciding time of day values of a plurality of apparatuses. The system includes a clock pulse generator for generating clock pulses having a predetermined interval, a TOD time of day timer controlled by the clock pulse, a time of day correction signal generator for generating a correction signal in a predetermined interval which is a multiple of the count cycle of the TOD timer. The clock pulse generator, the TOD timer, and the correction signal generator are arranged commonly for the apparatuses. The system also includes a counter which is incremented in response to the clock pulse, a time of day read and set unit for reading out current time of day information from the TOD timer in response to an external instruction and setting the time of day information in the counter, and a time of day correction unit for correcting the count of the counter in response to the correction signal. The counter, the time of day read and set unit, and the time of day correction unit are arranged in each of the apparatuses.
U.S. Pat. No. 5,504,878 to Coscarella et al. relates to a system for synchronizing multiple time of day clocks using a central time of day reference. The system includes a central time of day reference source integrated into a switch which interconnects I/O devices and host processors in a computer complex via fiber-optic links. A time reference oscillator in the switch serves to generate reference signals for the central reference and also provides a clock signal for the switch transmissions. Units to which the switch is attached obtain clock signals from their regenerated clocks which are synchronized to the time reference oscillator, and use the regenerated clock signals to control their local time-of-day counters. Each unit periodically transmits a signal to the switch requesting a dynamic connection to the switch-based central time-of-day reference in order to receive a time of day message.
U.S. Pat. No. 5,440,721 to Morgan et al. relates to a method and apparatus for controlling signal timing of cascaded signal processing units. Each of the signal processing units of a digital signal processing system is provided with a programmable timing delay unit having an identical programming interface to control the signal timing of its signal processing circuitry. A central timing unit is provided to the digital signal processing system to provide signal timing control inputs to the programmable timing delay units. A routine switcher is provided to the digital signal processing system to control configuration of the signal path, i.e. the order in which the signal is processed by all or a subset of the signal processing units of the digital signal processing system. The individual signal processing units are relieved from the burden of providing circuitry for timing control, delay equalization and timing derivation. The timing offsets for the individual signal processing units may be easily recomputed for any signal path, improving the reconfiguration flexibility of the digital signal processing system.
In some prior art parallel processor systems, event generated interrupts were relied upon and used to freeze time on a time board. Such algorithms are extremely difficult to implement in a massively parallel architecture.
There remains a need for a system and a method for determining the absolute time that events occur in a multi-processor system.